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Flash Memory SIMM
Mode register programming values are shown in Table 5-6.
:
Table 5-6. 100 MHz SDRAM Mode Register Programming
SDRAM
Address
Line 1
A11 (MSB)
A10
A9
SDRAM Mode Reg
Field
Reserved
Reserved
Opcode
Value
’0’
’0’
’0’ / ’1’
Meaning:
0 - Burst read & burst write (copy-back data cache)
1 - Burst read & single write (write-through data cache)
A8
A7
Reserved
Reserved
’0’
’0’
A6 - A4
A3
A2 - A0
CAS Latency
Burst Type
Burst Length
’011’
’0’
’010’
Data valid 3 clock cycles after CAS asserted
Sequential burst
4 Operand burst length
1
Actually SDRAMs’ A0 is connected to MPC8272 s’ A28 and so on.
5.6.2
SDRAM Refresh
The SDRAM is refreshed using its auto-refresh mode. Using the SDRAM machine one’s
periodic timer, an auto-refresh command is issued to the SDRAM every 8.2 μ sec, so that
all 4096 SDRAM rows are refreshed within specified 34 msec, while leaving an interval of
~30 msec of refresh redundancy within that window as a safety measure to cover for
possible delays in bus availability for the refresh controller.
5.7
Flash Memory SIMM
The MPC8272ADS is provided with 8 Mbytes of 95-nsec Flash memory SIMM, the
SM73228XG1JHBGO by Smart Modular Technology. This technology is composed of 4
LH28F016SCT-L95 chips by Sharp, arranged as 2M X 32 in a single bank. Support is given
also to 16 Mbytes and 32 Mbytes SIMMs. The Flash SIMM resides on an 80-pin SIMM
socket and is buffered from the 60X bus to reduce capacitive load over it.
To minimize use of the MPC8272’s chip-select lines, only one chip-select line (CS0 or CS4
if the E 2 PROM is using CS0) is used to select the Flash as a whole while distributing
chip-select lines among the module’s internal banks is done by on-board programmable
logic, according to the presence-detect lines of the Flash SIMM inserted to the
MPC8272ADS.
The access time of the Flash memory provided with the MPC8272ADS is 95 nsec.
However, devices with different delay are supported as well. By reading the delay section
Chapter 5. Module Design
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